Meta has partnered with AMD to showcase a type of memory that can be added onto servers using compute express link (CXL) technology.
Using this open standard for a high-speed processor-to-device and processor-to-memory interface, CXL memory can lead to far more efficient use of memory, saving hyperscalers money while boosting performance.
The demo board, which included an AMD EPYC 9004 Genoa processor, had four dual in-line memory module (DIMM) slots surrounding it, alongside a heat sink and fan. It also had a PCIe x16 connector, according to Serve the Home.
Ushering the age of CXL 2.0 memory
The CXL 2.0 memory expansion demo at the Open Compute Project (OCP) Global Summit 2023 was unusual in that it was built around an AMD chip, as opposed to Intel’s Xeon chip built on the Sapphire Rapids architecture.
One of the key promises of CXL memory is the possibility it’ll give hyperscalers to reuse DRAM, with memory controllers that can interface between DDR4 or DDR5 RAM and CXL potentially leading to major cost savings.
Essentially, as DDR4 memory begins to be phased out for DDR5 RAM, this may incur a significant cost investment for hyperscalers in managing their data centers. In fact, it’s perhaps one of the most significant costs here.
Using CXL memory could be a way for these companies to continue using any DDR4 RAM units they want to phase out, as add-on memory to augment newer units and beef up their server configurations.
There are several configurations of CXL memory in development, with Serve the Home also reporting on the aforementioned Intel chip being showcased alongside the Astera Labs CXL memory expansion card at SC22.
FADU, last month, also showcased a device that could augment a server with additional memory over CXL 2.0. Its Apollo CXL 20 switch was built to reduce latency and power consumption while being used.
Last year, Samsung also released a new version of its CXL DRAM, built with an ASIC CXL controller and packaging 512GB DDR5 DRAM to give servers a capacity boost.
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